Current semiconductor road-maps indicate that in about 10 years from now, processor chips will integrate 128 billion transistors. Unfortunately, these very small transistors will be difficult to manufacture with high precision, and be prone to fail. The challenge for designers will be how to build reliable, high-performance, low-power multi-core chips out of components that are intrinsically unreliable and exhibit a high variability in their properties.
The Principle Investigators (PIs) propose to address the challenge of parameter variation in these devices through a multidisciplinary effort that cuts across the architecture, CAD, and compiler areas. In the architecture area, the PIs will develop a novel model of variation-induced errors, a multi-core architecture that tolerates frequent errors in its normal operation, and a set of micro-architectural techniques that mitigate variation-induced errors. In the CAD area, the PIs will develop novel VLSI design methodologies that enable variation-aware design of Systems-on-Chip, including statistical timing analysis, pipeline re-timing, global wire pipelining, and clock skew variation reduction. Finally, in the software area, the PIs will develop a dynamic-optimization framework that characterizes the weakenesses of each core in a multi-core chip and shapes the instruction streams exposed to each core to reduce the frequency of errors, through advanced scheduling and dynamic compilation. Overall, the PIs hope to make fundamental advances toward cost-effective, robust high-performance computers.
