The persistent drive for increased performance and more functionality poses continuing challenges to computing. Reconfigurable computing is an alternative method to address these concerns: complex operations execute as hardware circuits made from reconfigurable logic instead of as slower sequential instructions on a programmable processor. This research examines the integration of reconfigurable logic into modern computing systems consisting of multiple processor cores, multiple levels of memory hierarchy, and virtual memory support. The project compares different cache-based and queue-based memory structures for use in novel memory interfaces that connect reconfigurable logic to system memory at various connection points within the memory hierarchy. New specialized memory controller designs optimized for reconfigurable logic and flexible enough for different application types will allocate these memory structures to the data needed by the reconfigurable logic. The memory controller designs will also support virtual memory to ensure memory protection, a necessary feature for today's computing systems. The research will evaluate these different memory interfaces and controllers to identify those best suited for reconfigurable computing, supporting the needed types of memory accesses, and providing the memory bandwidth performance required by circuits implemented in reconfigurable logic. The overall goal of the project is to elevate reconfigurable computing to a mainstream technique for complex computing systems, providing power savings and performance benefits to a wide variety of applications.
