The progress towards the scaling limits of silicon-based semiconductor technology has raised interest in non-silicon nano-devices such as carbon nano-tube field effect transistors (CNFETs). CNFETs offer tremendous opportunity due to high integration, but to successfully exploit them, designers must overcome the challenges of high variation in device parameters, high defect rates (opens or shorts) and high power density expected in CNFET based designs. Unfortunately, the device/circuit and architecture models and simulation tools that could facilitate the development and validation of circuits and architectures to overcome these challenges do not exist. The PI proposes to (a) develop an integrated device/circuit/architecture models and simulation software to enable designers to evaluate the performance, power and yield of nano-scale designs and (b) evaluate the benefits of several circuit and architecture innovations that address the key challenges (process variation, defects and power) of nano-scale design.
The tools and models developed as a part of this research will be made available to the research community through the Nanohub, developed at Purdue (www.nanohub.purdue.edu), which provides web-based access to computational tools and currently contains an array of simulation packages for semiconductor and molecular electronics. The availability of models will spur circuit and architecture innovations in the research community. The PI will develop new nano-electronic courses that will take an integrated approach to design. The courses will be based on the research findings and will be available for use. Participation of undergraduates, minorities and women will be actively encouraged through existing outreach platforms at Purdue such as LSAMP, Indiana as well as partnerships with other universities.
