The aim of the Tartan project is to create a high-performance energy-efficient computing system by understanding the space/time trade-off in spatial computing. Tartan eliminates the abstraction of the ISA allowing the compiler to communicate all information necessary to manage the execution of the application. Tartan compiles complete applications into application specific circuit. These circuits can be quite large and challenge the scalability of commercial CAD tools. In this context, Tartan harnesses new techniques based on the global critical path to focus the optimizer on the truly critical elements of the circuit. This new approach to optimization is applicable to the entire CAD community.
The underlying computing substrate in Tartan is a reconfigurable fabric. This fabric is regular and thus amenable to manufacturing with future nanoscale technologies. To improve power and to ensure that the reconfigurable fabric is tolerant of the expected parametric variation in such technologies the fabric is implemented using clockless self-timed circuits. The tools used to implement these circuits in Tartan should have broad applicability, hopefully eliminating one the roadblocks towards the adoption of self-timed circuits.
One of the driving forces behind today's economy is the growth of information technology, which itself is driven by the constantly increasing availability, and decreasing cost, of computing. Research into Tartan will help to continue these trends well into the future. Spatial computing has the potential to reduce design complexity, improve performance, improve energy efficiency, and support future nanoscale technologies.
