Today's communication appliances (e.g., PDA phones, GPS units, etc.) are a synergy of many technologies such as communication, video, image, and voice. What is common among these technologies is the fact that they exhibit (either by design, or by their intrinsic nature) a resiliency to errors. The user will hardly notice, for example, a dark pixel in an image or a video. When transmitting information wirelessly, on the other hand, errors are expected to occur over the air and receivers are designed to correct for such errors. By contrast, today's chips are designed to be error free and those chips that have non-fixable defects are discarded. While advanced semiconductor manufacturing technologies allow the fabrication of ever more complex Systems-on-Chip (SoCs) in small die sizes, it becomes economically impractical to achieve a 100% error-free chip design due to the large number of transistors per unit area as well as their proximity. For mobile applications, a paradigm shift away from 100% correctness is not only feasible, but seemingly unavoidable. The outcome of this project will result in a structured and scientific approach to exploit error-awareness across multiple abstraction levels of complex SoCs. A holistic integration of traditionally disparate (abstraction-level specific) techniques will allow system designers to rapidly explore complex chip implementations to meet a wide range of power, performance, and cost attributes. In the long term, this project will positively impact both ends of the producer-consumer chain: chip manufacturing companies will improve their productivity and become more competitive by allowing efficient fabrication of mobile chips; and consumers will benefit through lower cost mobile chips that allow longer operation of their mobile appliances while ensuring safe and correct execution of emerging applications.
