As the VLSI technology scales down to 45nm feature size and below, the lithography process no longer produces the ideal shape/dimension of circuit components in a silicon wafer. Geometrical parameter variations at 70nm technology can reach as much as 35%, and become increasingly severe as the feature size continues to decrease. The corresponding electrical parameter variations will significantly affect the performance and function of a VLSI circuit. Therefore, computing and analyzing the statistical properties of parasitic parameters in a silicon wafer become inevitable to the emerging nanometer scale VLSI technology. This grant aims to develop stochastic computational methods to address more general stochastic variables with distributions more realistic in nanometer VLSI technology.
This project will develop efficient algorithms using sparse grid spectral stochastic collocation method and compute interconnect capacitance and inductance using Wiener-Askey chaos basis and construct proper stochastic computational methods for non-Gaussian random variables. The intellectual merit comes from the development of sophisticated stochastic theories and efficient computing algorithms for the state-of-the-art engineering problems. This research will lay out basic guidelines and ideas and test the methods on realistic engineering problems. The broader impact of the research opens a new research direction in computing parasitic parameters with random process variations. The result of this research will have a great impact on the parasitic parameter extraction, circuit simulation and design of future nanometer scale VLSI circuits. It will lead to practical and efficient algorithms and CAD tools. Research of this project will be integrated into the graduate education of the Ph.D. students in applied mathematics and electrical engineering, and the developed software will be made public.
