Marios C. Papaefthymiou University of Michigan
Intellectual Merit The continuing scaling of semiconductor process technology brings about new challenges in the design of VLSI systems, while at the same time motivating new approaches for addressing them. Power density in high-end integrated systems has already reached performance-limiting levels. Increased device variability results in greater delay uncertainty, dictating the use of larger design margins and further limiting performance. Yet, silicon per device continues to decrease at exponential rates, enabling novel uses of silicon area. This research project will investigate next-generation design technologies for the realization of nanoscale VLSI systems in silicon. Specifically, this project will focus on the exploration of so-called charge recovery design technologies that enable operation at new levels of power-efficiency while reducing uncertainty due to device variability. In conventional VLSI design, capacitors are switched abruptly between supply and ground, experiencing high peak currents and dissipating all their stored energy as heat across resistive devices. Furthermore, device variability leads to significant uncertainty in the clock arrival times of conventional distribution networks with buffers. In contrast to conventional integrated systems, charge-recovery designs switch capacitors gradually, maintaining low peak currents and returning any undissipated energy back to the power supply. Therefore, charge-recovery designs can potentially lead to substantial reductions in switching power and gate leakage. Moreover, since they rely on buffer-less resonant clock distribution networks, charge-recovery designs are also expected to yield substantial reductions in clock delay uncertainty. The significant potential of charge recovery has so far remained untapped, as it represents a departure from established design practices. The main objective of this project is to explore and assess the potential of charge-recovery technologies, including circuitry, design methodologies, and computing architectures for realizing nanoscale silicon-based VLSI systems with unprecedented levels of power efficiency and performance. Broader Impacts The proposed research is expected to have a significant impact on the realization of next-generation VLSI systems, promoting discovery, teaching, and learning in novel design technologies that address key issues in nanoscale process nodes. Broader outcomes of the proposed effort include the integration of research activities into graduate-level courses, the development of lectures and projects for advanced undergraduate-level courses, as well as the direct involvement of electrical engineering and computer science majors through senior-level design projects. Consistent with the PI's proven record in promoting broad participation, the proposed research and education activities will include participants from underrepresented groups. A1
