Conventional top-down manufacturing faces serious challenges due to fundamental physical and economical constraints. Bottom-up approaches, in which integrated functional device structures are assembled from chemically synthesized nanoscale building blocks, such as carbon nanotubes (CNT) and nanowires, have the potential to revolutionize the fabrication of electronic systems for the future. Such nanosystems are by their nature very regular in structure and, therefore, suitable to implementation similar to Field Programmable Gate Arrays (FPGAs). Nanoelectronic circuits always have a certain percentage of defects as well as nanomaterial-specific variations over and above process variations introduced by lithography. Using simplified nanodevice assumptions and traditional scaled design flows will lead to suboptimal and impractical nanoFPGA designs and inaccurate system evaluation results. For nanotechnology to fulfill its promise, we need to understand and incorporate nano-specific design techniques, such as nanosystems modeling, statistical approaches and fault tolerant design, systematically from devices all the way up to systems. Motivated by this observation, this CAREER program proposes a fundamental, systematic and nano-centric design methodology for nanoscale FPGAs. The proposal includes the following four integrated design aspects: 1) Patterning: Designs novel and reliable architecture patterns, such as a new CNT-based one-time-configurable FPGA; 2) Modeling: Develops new device/wire/circuit models considering nanomaterial-specific variations, manufacturing limitations, and defects; 3) Synthesizing: Focuses on novel nano-centric synthesis techniques from the behavior level down to the physical design level; and 4) Evaluating: Builds a new parameterized nanoFPGA evaluation/exploration engine NanoEngine. The PI plans to develop a new interdisciplinary course incorporating nanomaterials fabrication, nanoelectronic principles, programmable ICs, and CAD. The PI has worked and will continue to reach out to K-12 students for micro/nano electronics education through short lecture series, Engineering Open House, and IEEE Teacher In-Service programs. He will also work with university organizations, such as Women in Engineering, to increase the participation of under-represented groups, especially female students. This project is especially compelling to undergraduate students, who are attracted to new technologies and may become the future leaders of nanoelectronic industry.
. It provides an infrastructure for evaluating various nanoscale FPGA designs through nanodevices modeling, nanocomponent patterning, new synthesis techniques, and variation and fault aware physical designs. It also emphasizes new design automation algorithms dealing with the design challenges for future high-density nanoscale circuits. During the last two years of the project, part of the grant was used to support students for developing the first SPICE-compatible compact models of GNRFETs (Graphene Nano-Ribbon Field-Effect Transistor). Overall, this project has led to almost 30 publications, including two book chapters and one best paper award. The main contributions are summarized below. First, we have provided early assessment and evaluation results of futuristic FPGA architectures that incorporate components built with nanomaterials and demonstrated their potential advantages over conventional CMOS technology. Two representative works are 3D nFPGA and FPCNA. Using unique features of FPGAs and a novel 3D stacking method enabled by the application of nanomaterials, 3D nFPGA obtains a 4x footprint reduction, a 2.6x performance gain with a small power overhead comparing to the traditional CMOS-based 2D FPGAs. In FPCNA, we defined novel CNT (carbon nanotube) and nanoswitch based components and characterized these components considering nano-specific process variations. FPCNA offers a 4.5× footprint reduction and a 2.67× performance gain compared to the baseline FPGA. These works demonstrated the unique potentials, advantages, as well as challenges (in terms of process variations and fault tolerance) of using nanomaterials to build future FPGA circuits, which can serve as valuable targets for nano-centric fabrications. Second, we studied new CAD techniques that are nano-centric, optimizing circuit power, reliability, and delay, with consideration of effects of process variations especially. We focused on the important design stages, namely, synthesis, placement, and routing. Some representative works include variation-aware and layout-driven high-level synthesis, soft error tolerant mapping algorithm for FPGAs with low power, variation-aware placement with multi-cycle statistical timing analysis for FPGAs, routing approach to reduce glitches in low power FPGAs, etc. Specifically, we developed FastYield, which is a new variation-aware high-level synthesis binding/module selection algorithm. It is connected with the lower levels of the design hierarchy through its inclusion of a timing-driven floorplanner guided by a statistical static timing analysis (SSTA) engine which is used to modify/enhance the synthesis solution. On average, FastYield achieves a clock period that is 14.5% smaller, and a performance yield gain of 78.9%, when compared to a variation-unaware algorithm. This is the first high-level synthesis binding/module selection algorithm that is layout-driven and variation aware. This work won the Best Paper Award at IEEE/ACM Asia and South Pacific Design Automation Conference in January 2009. Third, we developed the first parameterized, closed-form SPICE-compatible compact models for two varieties of GNRFETs, Metal-Oxide-Semiconducting-(MOS-)type and Schottky-Barrier-(SB-)type GNRFETs, and thoroughly discussed and explored their respective strengths in terms of delay, power, energy-delay product, and noise margin. For both types, the current and charge models closely match numerical TCAD simulations. In addition, the proposed models consider various design parameters and process variation effects, including transistor dimension, ribbon width, doping level, and graphene-specific edge roughness, which allows complete and thorough exploration and evaluation of GNRFET circuits under realistic process variations. In addition, we provided results assuming ideally fabricated GNRFET without variations and reported the gap of performances between ideal and non-ideal GNRFETs. The models were released online since July 2013. So far, there are 310 downloads from users worldwide. The models have been used by researchers from top universities, such as Stanford and UIUC. In addition, the models can be used in nanodevice manufacturing areas for experimental research in terms of achieving better device-level properties by controlling non-ideal factors during fabrication, which has been theoretically evaluated in our studies. Researchers can use the models to assess the potential advantages of tuning different device parameters. Finally, the project provided training opportunities for both graduate and undergraduate students. Quite a few students supported by this project have already graduated and joined important semiconductor companies, such as Intel, TI, and IBM. For broader impact, PI has visited Barkstall Elementary School in Champaign, Illinois to give short seminars to the students. He also regularly involved undergraduates in research group meetings, resulting in publications at top conferences. In addition, in the effort of outreach, a specific focus is given to empower underrepresented student groups. For example, the PI supervised two female undergraduate students for their senior thesis and three female graduate students for their Master or Ph.D. research. PI has lectured extensively on nanotechnology topics with invited talks and tutorials at numerous conferences, universities, and companies (DAC, DATE, ISLPED, ASPDAC, CMU, Berkeley, Stanford, NTU, IBM to name a few). He also organized special panels and sessions focusing on promises and challenges of nanotechnology (FPGA, SLIP, DATE).
