The recent industry?s shift to multi-core processor technology has literally made every modern-day desktop, sever, and laptop a parallel computing system. With multiple processing elements, or cores, integrated on a single chip, multi-core processors offer unprecedented, ubiquitously available parallel compute power. The paradigm change in computing has profound impacts on computer-aided design (CAD) of today?s ever complex nanoscale integrated circuits. This CAREER project intends to address the new computing challenges and opportunities as the current serial CAD practices transition to the future massively parallel paradigms, as dictated by the need to keep up with the increase in design complexity. The central approach of this work is to bring indispensable domain knowledge to parallel algorithm design so as to facilitate the most efficient use of emerging parallel hardware. A rich set of application-level coarse-grained parallelisms will be exploited under the single and multiple algorithm contexts to gain good parallel processing efficiency on multi-core and many-core platforms. A range of parallel CAD algorithms, encompassing key analysis, modeling and optimization steps in the design flow, will be developed. This work will lead to massively parallel CAD frameworks and tools that are critical to the design of a wide spectrum of nanometer digital, analog and mixed-signal integrated applications.
The computationally intensive nature of VLSI CAD makes it an important application domain of multi-core computing. The proposed work addresses the urgent need for developing parallel software applications and the resulting parallel computing paradigms are likely to be applicable to other science and engineering fields. As integral parts of this CAREER plan, education and research efforts will be integrated to provide research experience to undergraduate and graduate students. Research participation from minority and underrepresented student groups as well as K-12 education outreach will be actively promoted through existing research, outreach programs and inter-university collaborations. The PI will integrate the research outcomes of this project into undergraduate and graduate curriculum development and broadly disseminate them to academic, governmental and industrial sectors. Multidisciplinary, international and industrial collaborations will be formed to broaden the horizon of engineering students. Close industry ties will be leveraged to provide students with real-life experiences and facilitate immediate impacts of this work in industrial practice.
The industry’s shift to multi-core processor technology has literally made every modern-day desktop, sever, and laptop a parallel computing system. With multiple processing elements, or cores, integrated on a single chip, multi-core processors offer unprecedented, ubiquitously available parallel compute power. The overall goal of this project is to address nanometer VLSI design challenges by exploiting and developing scalable parallel CAD paradigms on modern multi-core platforms. The central approach of this work is to bring indispensable domain knowledge to parallel algorithm design so as to facilitate the most efficient use of current time parallel hardware. In this project, a variety of parallel paradigms including inter-algorithm and intra-algorithm parallelisms have been approached to deliver the required parallel performance for a key class of VLSI CAD challenges: Large-scale analog and RF circuit simulation: the key bottleneck of present analog/RF IC design flow; critical to a wide range of analog/mixed-signal/RF, clock generation/distribution circuits. Analysis and modeling of on-chip clock/power distribution networks: hampered by huge design complexity; critical to clock and power distribution, power delivery and regulation in high-performance and low-power chip designs. Sizing optimization of large power delivery networks: challenged by large solution space; critical for achieving high performance and power integrity. Analog/mixed-signal circuit verification: hampered by complex analog characteristics of the circuit and inherent computational challenges. Techniques for parallel performance modeling and runtime optimization: important for further optimization of the efficiency of parallel CAD algorithms running on diverse parallel platforms. Along the above lines, a coherent set of technical contributions have been made as summarized in the six journal papers and 12 conference papers published under this project. Broadly, the proposed work addresses the urgent need for developing high-performance compute-intensive software applications on modern multi-core processor platforms. The results of this work may be applicable to other science and engineering fields for which parallel computing is a key enabler. The PI has integrated the outcomes of this project into the graduate-level curriculum at Texas A&M University. The results of this project have been disseminated widely to academic and industrial sectors and the general public through technical publications, invited talks at conferences and industrial sites, and through a high-school teacher summer research program targeting minority high schools in Texas. Close industrial interaction has been established to provide the students with industrial exposure and help promote the adoption of this work in industry. 16 graduate students have participated in this project. Among these, five Ph. D. students and five M.S. students graduated and joined the US industry.
