The impact of communication on the performance of computer systems continues to grow both at the macro-level for blade servers and clusters of computers, and at the micro-level in multi-core processors. Meanwhile the tight on-chip power dissipation constraints have forced practically all major semiconductor companies to move to multi-core or chip multiprocessor (CMP) architectures. The emergence of CMPs has in turn placed increased challenges on the communications infrastructure as the growing number of processing cores integrated on each chip exacerbates the bandwidth requirements for both intra-chip and inter-chip communication.
This research aims to harness the recent extraordinary advances in nanoscale silicon photonic technologies for developing optical interconnection networks that address the critical bandwidth and power challenges of future CMP-based system. The insertion of photonic interconnection networks essentially changes the power scaling rules: once a photonic path is established, the data are transmitted end-to-end without the need for repeating, regeneration or buffering. This means that the energy for generating and receiving the data is only expended once per communication transaction anywhere across the computing system. The PIs will investigate the complete cohesive design of an on-chip optical interconnection network that employs nanoscale CMOS photonic devices and enables seamless off-chip communications to other CMP computing nodes and to external memory. System-wide optical interconnection network architectures will be specifically studied in the context of stream processing models of computation.
