Design of Integrated Circuits is highly impacted by the imperfections of the nano-scale manufacturing process. These imperfections translate into variations in the characteristics of devices and their interconnections. These variations tend to become more random and less systematic as technology further scales down into sub-45nm domain. Only partial statistical information might be known about these variations, such as their average, variance and range. Furthermore, depending on the stage in the hierarchical design flow, correlations in the variability of the components on the chip may be partially known. Given this partial information, robust performance estimation is required to obtain more predictability during the design process. A robust prediction should include all scenarios that match with the partially available variability data. The PI proposes to investigate the novel applications of two statistical and optimization-based approaches for robust modeling of the performance of VLSI circuits. The PI suggests investigating the applicability of these approaches for large circuit sizes and large number of die-to-die and within-die variations at different stages of the design flow.
Successful implementation of the proposed research allows a more predictable design flow which can make a significant contribution in the development of next generation Integrated Circuits by shortening design cycles, thereby allowing a faster time-to-market. Reducing the time-to-market can prevent losses of 5-10% magnitude per month in major manufacturing industries. In addition, the PI plans development of a graduate-level course which will likely appeal to the students outside the Computer Engineering area towards meeting their secondary and minor area requirements, at the University of Wisconsin-Madison. This research will catalyze the PI?s efforts to increase the diversity in engineering by encouraging women to study computer engineering and choose it as a career, either at industry or academia.
In today's technology, a single IC (e.g., the part of an iPhone that serves as the "brain") integrates billions of nano-scale components. These components are packed in a tiny space, yet provide amazingly diverse functionalities (multimedia, internet, phone) with high-speed, while consuming very low power. As the components continue to shrink in size, however, current technology faces steeper challenges in delivering the products of the next generation. A major challenge stems from the imperfections in IC fabrication: smaller components are less tolerant to these imperfections; their performance may turn out so poor that the IC may have to be entirely redesigned in order to meet the performance specs. This means delayed delivery of the final product, which means major loss of market opportunities. This research developed a mathematical framework for producing IC designs that are robust with respect to fabrication imperfections. A highlighting feature of this framework is that it requires only a limited knowledge of the manufacturing process--e.g., rather than relying on detailed information on manufacturing inaccuracies, it suffices in this framework to know only some bounds on the degree of imperfections. This is important since the designers often don't have access to detailed data on these inaccuracies -- they may not exist, or, third-party manufacturers may not release them. So the goal is to have a framework which is not only robust with respect to manufacturing errors, but also less dependent on the knowledge of them. The framework was developed by using theoretical results from the optimization area and exploring the extent and conditions for their applicability to this problem. In the presence of parameter variations, a crucial component in optimizing the performance of ICs is identification of critical paths.These are the paths within an IC which are part of the design and may result in the IC to fail during its lifetime, for example under certain workload and environmental conditions. This research proposed a technique to identify the "statistically-critical" paths under variations which were defined as the paths that are more likely to fail with respect to a designer’s performance goal. These paths can be useful for a more effective optimization of performance at the design stage prior to fabrication, or, they may be useful as pointers to localize the failure sites in the chip after fabrication. To identify the statistically-critical paths, the developed solution is based on computing tight lower and upper bounds for the performance of a sequence of connected gates and interconnects within the IC. A constant computational complexity is shown when updating the bounds and extending such a segment to a larger one, for example to become an entire path inside the IC. The bounds are used to efficiently extract the statistically-critical paths via a sweep of nodes and edges in the timing-graph corresponding to the design. Consequently, the developed path extraction framework can be paired with variability-driven performance optimization frameworks. The research was done with the aid of both graduate and undergraduate research assistants. The latter was done under the NSF-sponsored program Research Experiences for Undergraduates. Some of the infrastructure developed to conduct this research was used to enhance the teaching material in a graduate-level couse at the University of Wisconsin - Madison.
