The PIs propose the development of computer-aided design tools and circuit design techniques to analyze, monitor, and improve the reliability of integrated circuits in extremely scaled CMOS (i.e., sub-45nm) with significant levels of variability present. The desired outcome is a cohesive approach that improves chip lifetimes via both better estimation at design time (leading to reduced design margining, and therefore design times and costs) and circuit-based techniques that enable post-fabrication monitoring and improvement of robustness during the lifetime of a given die. The key components of this work include: 1) a tool that statistically determines expected chip-level reliability, 2) a theoretically rigorous approach that uses a small number of post-silicon measurements on a wafer to improve the reliability/performance characteristics of a larger set of chips, 3) new ultra-compact on-chip sensors to monitor reliability mechanisms with low overhead and compatibility with modern design methodologies, 4) a novel indirect measurement scheme based on the quiescent current draw of a chip to monitor for wearout, 5) design styles to combat very high intrinsic failure rates (e.g., 1 in 1000 devices fail).
The proposed strategy to improve reliability in highly variable nanoscale CMOS will facilitate sustained improvement in the performance and robustness of integrated circuits - a necessary condition for the continued evolution of semiconductor and information technology. In particular, higher functional and parametric yields will enable lower costs, which will largely benefit cost-constrained markets such as wireless/mobile. The impact of this work will be enhanced by leveraging promising undergraduate researchers, through improvements in curriculum, and through industrial interaction via class project mentoring. At the graduate level, this research will involve several students pursuing doctoral and master?s degrees, training them directly to conduct research in this area. The knowledge developed under the proposed research will be incorporated in VLSI CAD and circuits courses at both the undergraduate and graduate levels. Seminars and tutorials presented at the departmental level, at conferences, and at other universities will play an important role in disseminating the knowledge gained from this research, along with conventional publication in top journals and international conferences.
