A power distribution network in an IC is ubiquitous as seen by the internal logic, i.e., a power line is accessible to any internal node. This suggests the possibility of monitoring or controlling the logic value of any internal node through a power line by attaching a simple and nearly all-digital sensing/control circuit to the node. In other words, power line communications (PLC) in an IC provides designers with an inexpensive means to access to internal nodes, which can be useful for various applications, including test application time reduction for scan design, system debugging, fault diagnosis, monitoring transient logic values during built-in self test, and on-line testing. The research investigates the feasibility and practicality of PLC in ICs with circuit testing as the major target application. Upon successful execution of the project, the major technical accomplishments are as follows. (1) it suggests a new approach to address VLSI testing problems; (2) it investigates a new area, PLC at the IC level; and (3) it develops the necessary building blocks for PLC at the IC level. The use of power lines at the IC level has not been explored before, and it offers vast new applications in VLSI testing and other areas such as intra-/inter- chip level communications.
The outcomes of this research will be published in journals and proceedings and will be presented at technical conferences. The proposed research will also foster the integration of research and education and will be used to enhance the curriculum at the PI?s institution. This project provides an excellent opportunity to train undergraduate and underrepresented students in various electrical engineering fields, including VLSI testing, analog and mixed signal design, RFIC design, and circuit and system level simulation. An initial feasibility study for the proposed research has been conducted in close collaboration with a major US semiconductor company, and several other US semiconductor companies also have committed to collaborate in the proposed research. Close collaboration with those companies will provide a direct path to commercialization of the research at the successful conclusion of the project.
Prof. Dong Ha (PI) and his team investigated a new design-for-testability (DFT) approach to provide ubiquitous accessibility to internal nodes. The key idea for his team’s approach is dual use of power pins for data communications as well as power delivery. His team’s method intends to exploit a trend in VLSI, in which the number of pins, including power and ground pins, grows with deeper submicron technology. A power distribution network in an integrated circuit (IC) is ubiquitous as seen by the internal logic, i.e., a power line is accessible to any internal node. This suggests the possibility of monitoring or controlling the logic value of any internal node through a power line by attaching a simple and nearly all-digital sensing/control circuit to the node. The capability will be immensely useful for various applications, including test application time reduction for scan design, system debugging, fault diagnosis, monitoring transient logic values during built-in self-test, and on-line testing. The major goal of the project is to investigate the feasibility of the proposed method through from system level simulations and IC implementations. Project Findings The PI’s team performed various measurements on Intel microprocessors at an Intel site and studied Intel’s proprietary package and power distribution network (PDN) models. An RF signal and an offset of about 0.52 V DC was applied to a power pin of a 65 nm Pentium 4 microprocessor and a planar structure flip-chip LGA 775 package. To observe the signal on a power line, the backside of the chip was etched to make a tiny probe hole, and the signal on a power line of M2 metal layer was observed through the probe hole. The largest pass band and peak propagation is observed around 2 GHz over a 200 MHz band. As expected, the PDN is quite lossy with only about 5~7% of the signal passing through the PDN in narrow sporadic bands. Similar measurements were carried out on three different samples of the 45nm Core 2 Duo processors and two randomly picked locations on the core Vcc. The transfer characteristics also were measured on few samples of the cold 45nm Core 2 Duo processor’s PDN at different locations. The transfer characteristics also show narrow sporadic pass bands, where about 5~7% of the input signal passes through the PDN. There is a very little correlation between the transfer characteristics measured on the 65 nm Pentium PDN and the 45 nm Core 2 Duo PDN. Further, the large pass band observed around 2 GHz on the 65 nm Pentium PDN is not observed in the transfer characteristics of the 45 nm Core 2 Duo PDN. Expectedly, the pass bands move from one generation of processors to the next because of the difference in the package power plane design, on-chip power grid design as well as the difference in the thickness of the metal layers in different process technologies. Across different parts and different locations, the transfer characteristics essentially remain the same with minor differences. Since the pass bands can move from one generation of processors to the next, the PI’s team conclude that the pulses used for communications should cover entire spectrum of sporadic bands. The pulses should have ~ 2 GHz bandwidth, covering the frequency range 300 MHz to about 2.5 GHz, and so UWB pulses are the most suitable. The PI’s team designed and fabricated a PLC receiver with the major design objectives of a reliable operation under supply voltage fluctuations, droops, and noise. The proposed receiver adopts the binary amplitude shift keying (ASK), in which a signal level higher (lower) than VDD+VTH represents logic 1 (0), where VTH is a preset threshold voltage. The proposed PLC receiver consists of three blocks, a level shifter, a signal extractor, and a logic restorer. The level shifter lowers the DC level of the data signal from VDD to 0.5VDD. So that the data signal can be processed by the following signal extractor. The signal extractor removes the DC voltage from the data signal and amplifies the signal. The logic restorer, which is based on a Schmitt trigger, recovers logic values from the signal. The maximum allowable supply voltage droop was identified through simulations, and it was observed that the circuit can tolerate a supply voltage droop of 0.4 V from the nominal 1.8 V. The lowest supply voltage, at which the PLC receiver still could function correctly, was identified as 1.4 V through simulation. The proposed PLC receiver demonstrates that adoption of a hysteresis Schmitt trigger is highly effective to tolerate a large voltage droop.
