It is well known that ?Moore?s Law? states that computer chips will double their speed nearly every two years due to technological advancement. This advancement is typically due to the size of the transistors on the chip which are rapidly becoming as small as a nanometer (which is 1000 times thinner than a human hair). Since the transistors are smaller, more of them can be put on a chip which leads to faster computational times. Unfortunately, the processes needed to manufacturing these computer chips are highly complex and the final product often comes out defective or with lower performance than the original design. One particular manufacturing process, chemical mechanical polishing (CMP), is a major contributor to performance degradation and manufacturing costs. By combining chip defect testing models with advanced CMP computer models, the principal investigators (PIs) propose to research and develop a breakthrough computational methodology for predicting the impact of the CMP manufacturing process on the chip at the design stage.
CMP is a complex process in which the wafer surface that contains the chips is polished by pressing it against a rotating pad that is flooded with a slurry consisting of a fluid with abrasive nanoparticles. In order to accurately model this process, sophisticated computer models must be developed through collaborative research at the interface of electrical and computer engineering, applied physics, and mechanical engineering. A predictive computational tool resulting from this research would lead to radically improved concurrent engineering where chip designers are enabled to create bolder designs since they would be aware of the ramifications of CMP on their layouts. The resulting impact would be more sophisticated computer chip designs that exploit the most advanced materials which might normally be avoided due to the uncertainty of the effect of CMP on the materials. Due to the PIs on-going involvements with the recruitment and education of minority students, this work will also provide numerous opportunities to expose America?s next generation of engineering students at the pre-college and college levels to cutting-edge research in semiconductor technologies.
The computer processors or integrated circuits (ICs) that run our cell phones, computers, and automobiles get faster, as the transistors and associated electrical components of which they are comprised, get smaller. However, the defects that systematically occur during the manufacturing process play a larger role in adversely affecting the yield of the semiconductor wafers on which the computer processors reside. For example, a computer processor or IC is a device that is built thin layer by thin layer, and each layer needs to be atomically smooth before another layer is deposited. For this, chemical mechanical polishing (CMP) is used and this process may leave defects. CMP is a manufacturing process used to polish or planarize the newly deposited material on each of the layers on the wafer. Since many manufacturing processes for building devices on to each layer of the IC are dependent on CMP, they must be studied in a fashion where they are coupled. The study of CMP is critical due to its inherent effect on other manufacturing processes (photolithography, deposition, etching) and its ability to be related to the process defects which may occur. The best way to integrate the four manufacturing processes is to ‘virtually’ simulate the IC fabrication layer by layer, and allow the defects to evolve into the final IC. Thus, the ability to accurately model and couple CMP and the other processes through virtual fabrication would lead to higher yields, since the defects can be predicted and eliminated before the actual IC is manufactured. All of this would be done while saving money on costly trial-and-error from manufacturing costs. To date, the prominent physics-based models in the semiconductor literature have almost always been focused on either the macro-scale or the micro-scale. However, due to the multi-scale surface topography variation caused by manufacturing processes such as CMP, one cannot adequately model the micro-scale without taking the macro-scale information into consideration. Thus, a physics-based process modeling framework which can take in the IC layout (i.e., design) information as the input and then predict the location of the ensuing manufacturing process defects virtually before they actually happened was proposed and developed. This work used fundamental research from computer and mechanical engineering to develop the framework. The major findings from this project were that we were able to: (1) identify IC layout (design) features that are susceptible to become defected due to the semiconductor manufacturing process; (2) and, develop a methodology for identifying CMP-induced defect sites which will enhance the ability of IC test engineers to diagnose what and where a manufactured computer processor’s failure occurs.
