The proposed research will investigate the ?sizing? optimizations that underlie all practical tradeoffs of integrated-circuit area, delay and power metrics. The intellectual merit of our proposed research stems from its broad and multi-pronged attack on a fundamental type of design optimization. The PIs will investigate core aspects of optimization including technology strategy based on fast estimation of achievable solution quality, benchmarking of optimization heuristics and strengthening of iterative optimization heuristics by use of stronger move ?operators?. The PIs will also address fundamental changes to the optimization context such as the potential need for statistical optimization in a regime of uncontrollable manufacturing variability and the need for incremental optimization under the regime of evolving process models.
The broader impact of the proposed research lies in helping chip designers and manufacturers reduce design turnaround time in addition to IC area, delay and power metrics. This will enable the design of more complex and functional products within a given cost and power envelope; as such, our proposed research will have very substantial research and commercial impact. Other impacts will include open-source tools that will establish a baseline and foundation for further work by other research groups, preventing the wasted effort of reinventing the wheel that is endemic to experimental research today.
