This project focuses on coarse-grain power gating in ASIC designs, which switches entire blocks/rows of standard cells. This choice is due to lower cost and greater leakage savings of coarse-grain power gating compared to its fine-grain counterpart, which inserts the header or footer in each standard cell in the ASIC design library. The project results are expected to include the following: (i) Distributed sleep transistor placement and sizing; (ii) Sleep signal scheduling to minimize the peak current demand on wakeup; (iii) Mode transition energy minimization to enable more frequent mode transitions; (iv) Local sleep signal generation for autonomous power gating; and (v) Power gating to enable multiple power modes. This proposal aims to address each of these tasks by developing algorithmic or mathematical programming solutions to solving each step and by developing a design flow and prototype software tools that enable widespread adoption of this very interesting and important technology in the ASIC design.
The semiconductor industry?s $261 B in 2006 revenue does not accurately reflect its crucial role in enabling a $47 T ($61 T on a PPP basis) world economy to thrive and grow. This industry underpins the systems and technologies on which the people and governments of the world rely on for future prosperity. This industry is currently facing some extraordinary challenges, including variability of nano devices as well as excessive power dissipation in circuits and systems. In order for the industry to continue to expand and prosper, it is critical to address these challenges heads on. The proposed research takes on one of these two fundamental challenges, i.e., the ?power crisis?. The decisive impact of the proposed research will be the enablement of the CMOS scaling to continue unabated for the next 10-15 years. Moreover, the project will actively engage students both at graduate and undergraduate levels. For graduate students, active participation in the research work will enhance their creative and multidisciplinary thinking and prepare them for future independent work. The PI?s commitment of involving undergraduate students in carefully designed projects will help foster their long lasting enthusiasm in scientific research activities. Integration of research into curriculum development and classroom teaching will provide a powerful venue for the dissemination of research results that greatly compliments the traditional venues of conferences and archival journals.
Power gating, also known as Multi-threshold CMOS, is used to shut down certain power domains in a VLSI chip while leaving others active. Power shutdown can significantly reduce leakage power since many applications do not utilize all chip functions at all times. Using power gating can significantly extend the battery service life in battery-powered electronics, reduce packaging and cooling costs due to lower junction temperature in the chip, and possibly decelerate device aging due to a reduction in current demand and heat dissipation. The basic idea of power gating is to separate the power (VDD) or ground (VSS) supply rails from the standard cells using power switches. These switches are implemented using appropriately sized CMOS transistors. The switches can be either PMOS (header) or NMOS (footer) transistors that switch VDD or VSS, respectively. This proposal focused on coarse-grain power gating in ASIC designs, which switches entire blocks/rows of standard cells. This choice is due to lower cost and greater leakage savings of coarse-grain power gating compared to its fine-grain counterpart, which inserts the header or footer in each standard cell in the ASIC design library. Some of the key results and findings of our research are summarized below: We introduced a charge recycling power gating solution whereby charge is recycled between the virtual power and ground rails immediately after entering the sleep mode and just before wakeup. Simulation results demonstrate that the proposed method can save up to 43% of the dynamic energy wasted during mode transition while maintaining the wake up time of the original circuit. We developed a simple tri-modal CMOS switch cell that enables implementation of multimodal power gating, including active, data-retentive drowsy, and deep sleep modes. This switch allows one to take advantage of the ultra low leakage deep sleep mode, low leakage, but very fast wakeup, drowsy mode, and an additional low leakage data-retentive mode. Employing this switch in the data path of a high-performance multi-core processor resulted in an additional 20% power savings over the conventional bi-modal power gating solution. We invented two Static Random Access Memory (SRAM) cells that reduce the static power dissipation due to gate and sub-threshold leakage currents. The first cell structure results in reduced gate voltages for the NMOS pass transistors, and thus lowers the gate leakage current. The second cell structure makes use of PMOS pass transistors to lower the gate leakage current. In addition, dual threshold voltage technology with forward body biasing is utilized with this structure to reduce the subthreshold leakage while maintaining performance. We formulated the post sign-off leakage power optimization problem as a nonlinear mathematical program and solve it by using conjugate gradient (CG) method. We showed that by doing this optimization we can reduce the leakage power consumption by 34% on average in comparison with no power optimization after sign-off. The work was done at Synopsys jointly with their technical staff; all experiments were performed on the real industrial designs.
