Next-generation high-end machines will include interconnected computer nodes, each having heterogeneous accelerators and multi-core CPUs with complex memory hierarchy. They demand a programming model with a unified abstraction for programming dramatically different on-chip and off-chip parallel processing capabilities. None of the existing models is suitable for this need. The most fundamental challenge here is natural expression of parallelism in applications and efficient mapping of such parallelism to the hardware, including data distribution, locality, communication, synchronization, and load balancing.
This collaborative research between Syracuse University and Sandia Labs aims at developing an efficient programming model for high performance computing (HPC) applications using multi-core and heterogeneous processors. The specific goal of this study is to develop a high-level parallel programming abstraction with new high-level language constrctions, data types, and runtime library. Hardware features such as cores, memory hierarchy, processor heterogeneity, and interconnection will be embedded in the semantics of the language constructs and data types. The programming abstraction will guide the design and expression of parallel algorithms in the high-level language, mapped automatically onto the hardware for efficient execution. Users will be free from the low-level hardware details. The approaches include: memory virtualization,communication virtualization and processors virtualization.
