The emergence of multicore integrated circuits offers continued technological advances in computing through the on-chip integration of processors, graphics accelerators, memories, and other types of cores. Test solutions are needed to reduce cost and defect escapes, and to facilitate repair and reconfiguration through diagnosis. This project is therefore directed at new methods for comprehensive defect screening, optimization techniques for test delivery, and diagnosis flows to quickly identify faulty cores. It is structured around the following topics: (i) generation of high-quality tests to augment core-level patterns, including tests for power-management structures and clock-domain boundaries, and tests for the interconnect fabric and interfaces to the cores; (ii) theory and optimization tools for utilizing the interconnection fabric for test-data transportation; (iii) optimization methods to reduce the time needed for identifying faulty cores and clock domains. The project is being carried out in collaboration with partners at Intel and AMD.
This project will reduce test cost and defect levels, and lead to higher shipped-product quality for multicore-based systems. The test infrastructure will facilitate in-field testing, diagnosis, and dynamic reconfiguration through the use of spare cores. Resulting benefits for society include cheaper and reliable computing platforms for a wide range of applications. Undergraduate and graduate students will be prepared for the semiconductor industry. SRC Master?s Scholarships and PhD Fellowships will be used as recruitment tools, especially for under-represented groups. Tutorials at conferences and lectures at IEEE/ACM Chapters worldwide will lead to broad dissemination of research results.
This project was aimed at enhancing the dependability of integrated circuits that include a large number of embedded cores. Such "multi-core" chips are now common for personal computers, servers, and consumer electronics. The specific goal of this project was to develop design-for-testability solutions, and in particular target those parts of a multicore chip that are hard to test or not tested today during high-volume manufacturing. Test escapes can lead to field failures and customer returns. The first accomplishment of this project was the design of a power-switch architecture for leakage power reduction and the development associated DfT infrastructure. A generic method has been developed for trading-off system responsivess (for real-time operation) with leakage power savings. A US patent has resulted from this work (Patent no. 8,373,493). The main archival publication based on this work will appear soon in IEEE Transactions on VLSI Systems , and a second journal paper is currently under review. Several conference papers were published. A second accomplishment of this project lies in test scheduling innovations under various scenarios. Test scheduling refers to the order in which tests must be applied to reduce test time (and therefore manufacturing cost of chips). Techniques were developed for test scheduling for chips with dynamic voltage scaling for low power and multiple voltage islands (Nov 2012) and for chips that use a network-on-chip as the communicatio infrastructure ITC 2012). In addition, this project led to new techniques to understand clock-domain crossing (CDC) faults in system-on-chip (SoC) that use a large number of clock domains for better performance. The problem of "coverage gap" in such SoC chips has been studied and articulated, and test-generation, diagnosis, and repair solutions developed. These solutions allow for the detection of subtle timing faults and yield enhancement, whereby SoCs that exhibit CDC falures can be tuned and repaired post-fabrication. An archival paper on this work will be published soon in IEEE Transactions in CAD. Most of the research carried out in this project involved significant collaboration with the US semicoductor industry (Intel, Texas Instruments, AMD). The collaboration ranged from problem understanding, data for case studies, student internships, and co-authoring of papers. It is expected that most of the research breakthroughs will be transitioned to these companies. The grant supported two PhD students (one of these students graduated and joined Cisco Systems) and two short-term post-doc researchers. Students made presentations at major international conferences, and were prepared for the US semiconductor workforce. International collaboration was established with researchers in Greece.
