Fractional-N phase locked loops (PLLs) are critical components in most modern wireless communication systems including cellular telephones and wireless local area networks. Unfortunately, the error introduced by conventional PLLs contains period disturbances referred to as spurious tones, which only can be suppressed sufficiently for typical wireless applications with techniques that increase power consumption and cost. Furthermore, these techniques become less effective as integrated circuit (IC) technology continues to scale to smaller dimensions. Therefore, the spurious tone problem negatively affects power consumption, cost, and manufacturability of wireless communication systems, and the problem gets worse as IC technology scales with Moore?s Law. The ÄÓ modulator in a conventional PLL is the fundamental cause of spurious tones. The spurious tones are induced when the ÄÓ modulator?s quantization noise is subjected to nonlinearity from non-ideal circuit behavior in the PLL. The goal of this research is to develop a ÄÓ modulator replacement, called a successive requantizer, that avoids this problem. The successive requantizer has a different principle of operation than a ÄÓ modulator and its quantization noise is much less susceptible to nonlinearity-induced spurious tones. The research tasks are 1) to further develop the theory underlying successive requantizers to improve their performance, 2) to investigate how PLLs can be optimized at the circuit level to take advantage of the reduced sensitivity to nonlinear distortion offered by successive requantizers, and 3) to develop a proof-of-concept fractional-N PLL IC enabled by the theoretical results of the project that is compliant with a demanding wireless standard such as IEEE 802.16 and exceeds the present state of the art in terms of minimizing power consumption and circuit area.
