This project addresses critical questions relevant to the successful realization of nanoelectronics based computing platforms. The promised higher density, lower power, and faster operation of nanoelectronics devices is attracting increasing interest. Two of the remaining major roadblocks to the creation of nanoscale computational structures, however, are very high levels of defects and process variations. While the small size of nanostructures and their self-assembly based manufacturing provide great advantages, they also cause them to be very vulnerable to defects and parameter variations---much more so than conventional CMOS. The high defect rates require a layered approach for fault tolerance and typically involve incorporating carefully targeted redundancy at multiple system levels. In addition to defects, even tiny variations in the manufacturing process can lead to very substantial variations in the actual values of key parameters, such as circuit delay. The purpose of this award is to develop a comprehensive methodology to efficiently use redundancy in nanofabrics to ameliorate the effects of both high defect levels and circuit delay variations. The methodology that will be developed will assist designers with a set of well-tested approaches to provide resilience in the face of manufacturing defects and process variations. In educational terms, this project will contribute to the training of undergraduate and graduate students in the art of physical nanofabrics, nanoscale computer architecture, and circuit design for the future nano-technologies.
