On-chip variability monitoring and post-silicon tuning have emerged as a joint-strategy to combat the deleterious effects of nanoscale process variations, to maintain the aggressive scaling of integrated circuits (ICs). However, the design overhead (e.g., die area, power consumption, etc.) of these new techniques is a growing problem as devices continue to shrink, and the relative magnitude of critical process fluctuations continues to grow. This project proposes to develop a novel statistical framework called virtual probe (VP) to minimize the overhead of variability monitoring and post-silicon tuning. VP accurately predicts full-chip spatial variation from the smallest possible set of measurement data, thereby enabling lowest-cost / highest-accuracy silicon testing, characterization and tuning as IC technologies move further into the nanoscale regime.
The proposed project aims to create a radically improved platform for on-chip statistical monitoring and tuning of large-scale digital ICs; it is expected to yield 5-10 times performance improvement for advanced ICs in a broad range of applications, from consumer electronics to aerospace controllers. In addition, the proposed mathematical framework is applicable to many other scientific and engineering problems and, hence, offers a new avenue to study and understand these. Finally, given its broad coverage over multiple research areas, the proposed project motivates close collaboration among statistician, computer scientists and circuit designers, thereby creating enormous opportunities for interdisciplinary innovations. The interdisciplinary nature of this project also offers an excellent opportunity to train the next generation of U.S. researchers in multiple science and engineering domains.
