Present-day integrated circuits are expected to deliver high-quality/high-performance levels under ever-diminishing power budgets. Due to quadratic dependence of power on voltage, supply voltage scaling has been investigated as an effective method to reduce power. However, supply scaling increases the delays in all computation paths and can result in incorrect or incomplete computation of certain paths. Besides power dissipation, process variations also pose a major design concern with technology scaling. Supply voltage can be scaled-up or logic gates can be up-sized to prevent delay failures and to achieve higher parametric yield. However, such techniques come at the cost of increased power and/or die area. Meeting the contradictory requirements of high yield, low power and high quality are becoming exceedingly challenging in nanometer designs. Hence, there is a need for a scalable design methodology in which minimal output quality degradation is achieved under changing power constraints and process conditions. In addition, for a prescribed power consumption level and process, design methodology must take into account the effects of input signal noise and distortion on the fidelity of the Digital Signal Processing (DSP) computation and ensure that graceful output quality degradation is achieved under varying degrees of noise and distortion through proper algorithm and hardware design.
The research involves development of a systematic methodology for reorganizing (transforming) algorithmic level computations, data and underlying hardware in such a way that minimum performance degradation in DSP systems is achieved under reduced power supply, increased process variations and reduced input signal quality. It has been observed that for DSP applications/systems, all computations are not equally important in shaping the output response. This information is exploited by the investigators to develop suitable algorithms/architectures that provide the ?right? trade-offs between output quality vs. energy consumption (supply scaling) vs. parametric yield due to process variations vs. input signal noise. To address resilience to process variations, the investigators identify the significant/not-so-significant components of such systems based on output sensitivities. Under such a scenario, with scaled supply voltage and/or parameter variations, if there are potential delay failures in some paths, only the less-significant computations are affected. In other words, using carefully designed algorithms and architectures, the investigators provide unequal error protection (under voltage over-scaling) to significant/not-so-significant computation elements, thereby achieving large improvements in power dissipation with graceful degradation in output signal quality.
