Multi-core processors provide the only way to continue improving peak performance without much increase in the power consumption. However, there are serious challenges not only in expressing all the parallelism in the application, but also in exploiting the available parallelism by efficient application management on modern multi-core architectures. These challenges are only compounded by the trend of the absence of memory virtualization in the hardware, that is observed in futuristic processors, like the IBM Cell, and the Intel experimental 80-core processor. Memory management cannot be supported in hardware, because cache coherency protocols do not scale to 100s or 1000s of cores, and also because memory management in hardware consumes significant energy. Memory management in software can exploit application and data characteristics to reduce the overhead, however, it increases the burden of the application programmer. This project aims to develop tools and techniques to automatically manage the limited local memories present in each of the cores of a multi-core processor. In addition to power-efficient execution, the main objective of the project is to relieve the application programmer of the burden of carefully crafting the application, dividing and mapping it onto the cores to ensure its correct execution and portability.
