Future multi-core microprocessors will be capable of deconfiguring faulty units in order to permit continued operation in the presence of wear-out failures. However, the unforeseen downside is pipeline imbalance in which other portions of the pipeline are now overprovisioned with respect to the deconfigured functionality. Such an imbalance leads to sub-optimal chip-wide power provisioning, since power is now allocated to pipeline functions that no longer provide the benefit they did with a fully functioning chip.
This research proposes to dynamically redistribute the chip power under pipeline imbalances that arise from deconfiguring faulty units. Through rebalancing -- achieved by temporary, symbiotic deconfiguration of additional functionality within the degraded core -- power is harnessed for use elsewhere on the chip. This additional power is dynamically transferred to portions of the multi-core chip that can realize a performance boost from turning on previously dormant microarchitectural features. The technical deliverables of this project will be: (1) a novel resilient multi-core system architecture -- including dynamic power redistribution management algorithms -- that achieves much higher performance than one that is oblivious to pipeline imbalances; and (2) detailed simulations that quantify this performance advantage for various multi-core workloads.
The broader impacts of this project relate to integrated research and education, enhanced infrastructure for research, broad dissemination of results, and potential societal impact. Furthermore, the PI will recruit women and underrepresented minority students to work on the project.
