Timing errors resulting from process variability, manufacturing defects, and aging effects in scaled CMOS technologies are an important failure mode that impact the reliability of multi-level control logic in commodity mainstream computer systems. This project makes a case for lookahead logic circuits based on the principles of prefix computation to address performance, reliability, and power challenges posed by timing errors in multi-level control logic. Lookahead logic circuits promise low-cost logic-only solutions that can be used to (i) increase performance and/or yield by reducing logic delay, (ii) improve logic circuit robustness to timing errors by masking them, (ii) lower power consumption by increasing the scope of aggressive dynamic voltage and frequency scaling, and (iv) enable more effective and targeted post-silicon debug and online wearout prediction. The research will formalize the principles of lookahead-based function decomposition and prefix-based computation for multi-level logic circuits, develop logic synthesis and design solutions for lookahead logic, and investigate its applications in the context of superscalar and multi-threaded processor design.
A major impact of this research is to enable ubiquitous low-cost highly reliable computing, by expanding its reach to domains, where custom solutions are economically infeasible. An integrated outcome of this project is the development of a testbed and web-based resources to facilitate research in reliable system design. Through course development and collaborations with industrial partners, the research will contribute to education, community resource development and technology transfer to industry.
