Dynamic random access memory (DRAM) has been used as the main memory in computer systems for decades. However, DRAM technologies are facing both scalability and power issues. With the superior scalability, phase-change memory (PCM) has become an attractive DRAM alternative to implement high-capacity, ultra-dense main memory systems. Recent advances in nano-scale material engineering have also enabled fabricating phase change memory using nano-scale structures (e.g. nano-wire), which exhibit ultra-low programming power than the conventional thin-film based substrates. Although technology scaling and advanced material engineering provide smaller and denser devices, they make architecting reliable, power-efficient and high-performance phase change memory systems increasingly challenging. If left unattended, these challenges will soon become showstoppers of future phase change memory systems by either preventing them from scaling down to smaller feature sizes or resulting in the inefficient operation of these systems. This collaborative research project aims to improve the efficiency of phase change memory systems as the underlying processing technology scaling continues, including: (1) Cross-layer process variation characterization, modeling and mitigation for phase change memory (2) Nano-wire based PCM design exploration and (3) Resistance drift resilient phase change memory system. In addition, this project will develop a comprehensive full-system simulation infrastructure that consists of PCM device/array/architecture multi-scale models and architecture/OS techniques that will allow the computer architecture design community to study the trade offs and optimizations of employing emerging phase change based memory systems in light of advanced process technology and material engineering. This collaborative research project will facilitate ultra-density, low-power and reliable phase change based non-volatile memory systems to most effectively leverage emerging nano-scale material and fabrication technologies to tackle the grand "Memory Wall" challenge faced in today's computer design community. It can greatly contribute to enabling high-performance computing to stay on track with its historic scaling as the number of CPU cores increases and workloads become more memory intensive, and hence benefit numerous real-life applications running from high-end servers to low-end embedded systems. This collaborative research project will also contribute to society through engaging under-represented groups, research infrastructure dissemination for education and training, and outreach to non-volatile memory design industries.
