Over the past few decades, the semiconductor industry has been primarily driven by increasing performance and transistor counts. The increase in system design complexity increases the importance and complexity of test and verification. The need for on-line testing of complex CMOS systems and to reduce the off-line test cost, mandate a systematic and standardized test and verification methodology. The future test and verification methodology will use a modular architecture, a programmable topology to address time varying test requirements, and a centralized control scheme for simple access and reconfiguration by operating software. The proposed test and verification architecture will utilize low-cost low temperature poly-Si (LTPS) thin film transistor (TFT) circuits on glass or plastic substrate stacked on top of a silicon substrate. An on-line test control module transmits test vectors to multiple TFT test circuits on glass/plastic substrate through RF wireless inductive links. The wireless link allows both parallel (broadcasting) and series transmissions. Power and timing (clock) signals can be wirelessly transmitted along with the test vectors, if required. The TFT test circuits evaluate and monitor the underlying silicon CMOS circuits through flip-chip bump contacts and transmit the collected response data back to the test control module. The proposed architecture is: (1) low-cost, (2) modular, (3) can apply programmable test vectors for time varying on-line tests, and (4) allows easy access and control by operating software. The TFTs on which the proposed test circuits would reside, should have reasonable performance and work with CMOS-compatible supply voltages. The proposed research will also investigate and develop optimized TFT structures and passives for CMOS-compatible operations and suitable for 3D integration with standard CMOS systems.

The need for low-cost low-power high-performance electronics is rapidly growing. It is possible to optimize TFT devices on flexible substrates to achieve reasonable performance with low-power dissipation, with CMOS compatible supply voltage. Traditionally, TFTs have been used in high voltage display applications where speed is not important. This research is therefore, a novel way of optimizing and using TFTs for higher performance and lower-power, opening up a plethora of applications such as low-power DSPs and sensors based on the TFT-CMOS hybrid architecture in addition to the low-cost test/verification application. The ability to implement ?higher-performance? TFTs on flexible substrate with a low-cost process also helps in embedding such electronics/sensors on materials such as clothes, automobiles, planes, etc. Given the possibilities with such approaches, there is a pressing need to develop such devices and corresponding models and simulation tools to harness the unique characteristics of these devices to achieve high-yield, reliable performance and low-power dissipation. This will enhance our understanding of flexible electronics from device, circuit, and architecture perspectives and open the door for ?more than Moore? applications.

Project Start
Project End
Budget Start
Budget End
Support Year
Fiscal Year
Total Cost
Indirect Cost
Purdue University
West Lafayette
United States
Zip Code