The availability of parallelism in single-chip microprocessors has increased exponentially over the last five years, as process technology parameters have led microprocessors designers to transition from single core to multi-core designs. This trend is certain to continue; designs with hundreds and even thousands of cores on a single chip are envisioned in future. These chips, often referred to as manycore processors, offer the opportunity to greatly increase our computational capabilities through continued exploitation of Moore's Law. However, with them the deep and difficult goals of programmability and energy efficiency have emerged as two of the central research challenges in computer engineering today.
Recently, issues in programming multi- and many- core chips have led many members of the research community to believe that addressing the multi-core programmability crisis is one of the most critical issues in computer science research today. The goal of making multi-, and many- core architectures more useful calls for new approaches that will greatly reduce the programmer effort and skill required to attain good performance across a wide variety of programs. This research examines a manycore system called Feather, which attacks these programmability issues through a combination of automatic parallelization and novel architectural techniques. Feather focuses on heavily numerical applications, and is programmed using high level languages. Feather combines a tunable compiler, a run-time system, and an architecture into a system that seeks to ease performance brittleness and programmability issues for numerical codes on manycore systems.
