Complexity and nano-scale non-idealities of modern electronic systems make it hard to achieve a high degree of validation before fabrication. Post-silicon debug of malfunctions is further complicated due to the limited chip interface with the outside world. The existing debug process is predominantly manual, time-consuming, and involves expensive equipments. Consequently, time-to-market and profit are directly at stake.
This proposal proposes a methodology for automation of the post-silicon debug process. It relies on embedding and measuring special design structures to verify the "health" of the system, and on analysis methods using these measurements, to debug the cause of errors. Specifically, the attention is towards those malfunctions that manifest themselves in the form of timing errors, which cause setup and hold time violations in logic, and are the most cumbersome type of error to analyze. The proposed methodology identifies on-chip measurement sites of combinational and sequential logic, and analysis methods which are either real-time and workload-dependent, or static and based on guard-band computation, at both design and post-silicon stages.
The education goals are improving teaching, diversity, and preparation of undergraduate and graduate students for the engineering practice and research. The following three tasks are proposed: 1) developing and teaching a case study based on the "One Laptop Per Child" project in an inter-disciplinary freshmen-level course; 2) engaging undergraduate students and developing programming assignments to enhance teaching in the VLSI-CAD area; 3) utilizing various resources to recruit women and minorities, and to train undergraduate and graduate students.
