Future integrated circuits will contain tens, hundreds, or possibly even a thousand cores per chip. However, the scaling techniques that will make this possible also make the underlying circuit fabric less reliable-leading to increased wearout and defects that cannot be detected at manufacturing. In response, the PI proposes fundamental research for generating new test sets on-chip to identify failing cores. The tests will be created "on-the-fly" and dynamically targeted to the most critical areas of a core. Some key portions of the proposed research involve the creation and verification of hardware monitors for determining which faults are most important for the user's applications, the diagnostic use of online error detection hardware to pinpoint locations that caused previous failures, and the analysis and development of protocols to efficiently create and transport tests in a network-on-chip environment.
The great performance advantages of future multi-core devices will remain unrealized if the reliability of those devices cannot be trusted. The proposed research investigates critical tools for promoting that reliability. The integrated education plan provides research opportunities for students at multiple levels?from high school to graduate school?including students from underrepresented groups. In addition to recruiting undergraduates from Brown, the PI plans to work with the CRA-W DREU (Distributed Research Experiences for Undergraduates) program to host visiting female undergraduates for summer research. The PI will also recruit high school students from the Providence Public Schools, many of whom are members of underrepresented groups, for summer research through the Brown GK-12 program.
