Real-time systems ranging from aircraft and nuclear power plant controllers to video games and graphics animations have become an increasingly important part of our society. For real-time applications to harness the full potential of multicore chips, the execution time of multicore processors must be predictable, which is particularly crucial for hard real-time and safety-critical systems. Unfortunately, current multicore architectures are designed for maximizing average-case performance, and some architectural features such as shared caches can significantly affect the worst-case performance, making accurate WCET (Worst-Case Execution Time) analysis extremely difficult, if not impossible. This harmful impact on time predictability will become even more severe in emerging manycore processors.
This proposal attempts to design a time-predictable yet high-performance multicore/manycore architecture to provide scalable and predictable performance for future high-performance real-time applications. In addition to systematic analysis of existing multicore architectural features that can severely affect time predictability of computing, this project will develop a variety of time-predictable cache and memory architectures to ensure time predictability. This project will also implement TMulticore on a FPGA to develop deep understanding of real design constraints for time-predictable multicore/manycore chips.
The success of this project is expected to enable the safe and reliable use of multicore/manycore processors for a wide variety of real-time applications to enhance their performance and energy efficiency with deterministic computation time. This project will involve both undergraduate and graduate students in the design, implementation, and evaluation of the proposed TMulticore processor. In particular, the PI is committed to attracting underrepresented students into this project. In addition, funding of this project will greatly facilitate the growth of the new Ph.D. program in Electrical and Computer Engineering at the Southern Illinois university.
Multicore and manycore processors can potentially benefit hard real-time or mixed systems that require higher throughput and lower energy consumption. However, most today's multicore/manycore architectures are designed for general-purpose applications, which can be harmful to hard real-time systems that require time predictabiilty. In this project, we systematically analyze the time un-predictability of multicore/manycore architectures. We then explore a number of software-assisted or pure hardware-based cache and memory architectures that can improve both time predictability and performance (or energy efficiency). Such architectures can signficantly reduce the complexity of worst-case execution time (WCET) analysis for multicore/manycore processors. We have implemented and evaluated the proposed time-predictable architectures through simulation. We have also develop a WCET analyzer to estimate the WCET of the shared cache and multicore processors. Our evaluation shows that the WCET of hard real-time applications can be adequately reduced by the proposed architectures while at the same time the average-case performance can be improved substantially. The designed time-predictable architectures make it possible to safely and reliably use multicore/manycore processors for a variety of high-end real-time applications such as automobile and avionics control systems. This project has invovled both graduate and undergraduate students in the design, implementation, and evaluation of the proposed time-predictable architectures. Some topics derived from this project have also been introduced into a graduate-level course EGRE 631: Real-Time and Embedded Systems at Virginia Commonwealth University.
