This project aims at a systematic approach that integrates multi-level IC design automation flow by leveraging the parallel computational power in current and upcoming multi-core/many-core processors. The main challenge in this approach is to provide responsive high-level design decisions while incurring the massive computational cost of lower-level design algorithms. Fortunately, recent trends in processor architectures provide a solution. Compared with traditional uniprocessor systems, emerging multi-core/many-core microprocessors have far more computational power but limited global memory access capabilities. Parallel computational power may make it possible to break the boundaries of the existing IC design hierarchy and to vertically integrate the IC optimization fow. The potential benefits of an integrated solution are significant - accurate high-level design decisions become possible as low-level design details are derived concurrently, and low-level designs can also greatly benefit from high-quality high-level decisions. Together, an efficient and high-quality design flow becomes feasible, making design closure faster, thus saving time and reducing costs.
The proposed work has the potential to overcome the key limitations of existing hierarchical IC CAD technologies and enable new IC design automation solutions, which in turn can benefit the IC and semiconductor industry. The PIs will work together with their industrial collaborators to develop and commercialize the proposed work. The project will have beneficial impact on education. The PIs intend to educate the next generation of software developers and practicing engineers in the design and innovation of IC design automation and parallel computing.
