One of the fundamental challenges facing the processor industry today is in continuing to address performance and scalability demands given the constraints of both energy and programmer efficiency. This CAREER project builds upon recently-introduced fused designs, which incorporate conventional microprocessors and graphics processors in the same package, in order to address these challenges through the development of more programmable, flexible, scalable, and secure hybrid architectures. Towards this long-term goal, this project investigates techniques that minimize limitations of the traditional coprocessing model, including performance bottlenecks, vulnerable shared memory spaces, and inflexible resource management.

Specifically, this project explores thread divergence caused by complex control-flow and memory access, thread migration between cores, hardware accelerator design for tasks beyond traditional graphics processing, and adding security safeguards to match what is currently available on conventional microprocessors. In addition, this project also examines a variety of instruction set extensions, accelerator architectures, and models of computation that have the potential to lead to significant efficiency and programmer flexibility improvements. The expected impact is that this CAREER project will one day bear fruit in the form of another new segment of the computing industry, one that specializes in hybrid architectures that can scale to thousands of independent threads, while maintaining the capabilities of a traditional multi-user operating system and middleware. Broadly speaking, by advancing the state-of-the-art in computer architecture, this research will lead to improvements in consumer devices in terms of size and form factor, energy efficiency and battery life, and complexity and graphical fidelity of supported applications. Similarly, the usage of these architectures to enable continued performance scaling has the potential to have wide-ranging societal impact, through the advancement of those fields (e.g. bioinformatics, climate modeling, business intelligence) that utilize high-performance computing to enable innovative discovery. This project also includes a focus on expanding an existing course that the PI has developed, that takes a novel approach in introducing graphics processing and architecture from a hardware design perspective.

Agency
National Science Foundation (NSF)
Institute
Division of Computer and Communication Foundations (CCF)
Application #
1149539
Program Officer
Yuanyuan Yang
Project Start
Project End
Budget Start
2012-04-01
Budget End
2019-08-31
Support Year
Fiscal Year
2011
Total Cost
$466,312
Indirect Cost
Name
Iowa State University
Department
Type
DUNS #
City
Ames
State
IA
Country
United States
Zip Code
50011