Multi-core processors with hundreds of embedded functional blocks are designed to achieve unprecedented performance benefits for a wide variety of applications such as graphics, financial and scientific modeling, networking, multimedia and wireless infrastructure. The Network-on-Chip (NoC) is an enabling methodology to integrate many embedded cores on a single die. However, with growing levels of integration traditional NoCs suffer from high latency and energy dissipation in on-chip data transfer due to conventional metal/dielectric based interconnects. The wireless NoC (WiNoC) simultaneously addresses the latency, power consumption and interconnect routing problems of conventional NoCs by replacing multi-hop wired links with high-bandwidth single-hop long-range wireless channels. Recent investigations have characterized silicon integrated on-chip antennas operating in the millimeter (mm)-wave range of 50-110 GHz, and this is now a viable technology. Coupled with significant advances in mm-wave transceiver design, this development opens up new research opportunities for designing high bandwidth and low power WiNoCs.

The proposed research will develop a cross-layer design methodology for an on-chip wireless micro-network. Suitable physical, data link and network layer protocols will be developed for the WiNoC. The expected contribution of this work is the development and demonstration of broadband and integrable mm-wave WiNoCs. The transformational aspect of this proposal lies in addressing the on-chip interconnect problem from a fundamentally new perspective, namely by developing a broadband millimeter wave wireless network at the micro/nanoscale, as opposed to pursuing incremental improvements in traditional wired interconnects. By bringing wireless networking to the on-chip environment, the proposed research will introduce a paradigm shift in the design of multi-core chips.

The proposed research will facilitate the education of undergraduate and graduate students by allowing them to apply classroom knowledge to a research problem requiring hardware, software and theoretical expertise. Such expertise will be developed in both university and industrial laboratory settings using state-of-the-art test equipment and computing facilities, and will ultimately be necessary to maintain the technological leadership of the United States. Students from various underrepresented groups, including women, African Americans and Hispanics, will be engaged in this project. The project's educational impacts will be complemented by the positive effect that the research outcomes are expected to have on society as a whole.

Agency
National Science Foundation (NSF)
Institute
Division of Computer and Communication Foundations (CCF)
Application #
1162063
Program Officer
Yuanyuan Yang
Project Start
Project End
Budget Start
2012-06-01
Budget End
2018-05-31
Support Year
Fiscal Year
2011
Total Cost
$225,000
Indirect Cost
Name
Georgia Tech Research Corporation
Department
Type
DUNS #
City
Atlanta
State
GA
Country
United States
Zip Code
30332