Smart phones, tablet computers, and other mobile devices are transforming the way people work, play, and interact. Their mobility, connection to the cloud, and integration of sensors, computation and communication have inspired unique applications unforeseen just a short time ago. The future holds even greater promise, as applications fuse diverse inputs to deliver new levels of situation awareness and embedded intelligence. To fuel this rapidly growing market, the processors that power mobile devices must be designed more quickly than processors in conventional computers, even as the complexity of mobile processors approaches that of desktop and server processors. Product development is accelerated by licensing hardware descriptions of the latest processors - called soft cores - from third parties, and integrating them with proprietary designs into an overall system-on-chip. Unfortunately, there is an additional step that erodes the productivity gains won by licensing soft cores. A soft core must be converted into a hard core, i.e., a circuit layout that can be fabricated in a semiconductor foundry. Producing a high-quality layout is a painstaking, manual process requiring niche expertise. Alternatively, automated synthesis and place-and-route (SPR) tools can be used, but they produce poor layouts with sub-par performance and power consumption.
This research combines the convenience of automated layout with the quality of manual layout. The key innovation is to not compromise on automation - SPR must be used - but rather to modify the design of mobile processors so that SPR is able to produce a quality layout on par with manual layout. That is, the mobile processor is designed with the knowledge that SPR is going to be used. This new paradigm is called Design for Competitive Automated Layout (DCAL). DCAL applies a novel regimen of design strategies at multiple levels that enables SPR to produce competitive layouts. A common theme across all levels is to restructure or eliminate sources of processor complexity that SPR handles poorly. (1) Circuit-level DCAL: Highly-ported memory structures traditionally require intense manual layout. Making matters worse, there are many of them in a modern processor. These are restructured to achieve quality layouts without manual effort. (2) Microarchitecture-level DCAL: The most challenging processor units are restructured so that aggressive circuit and layout optimizations for meeting timing closure are rendered unnecessary. (3) Core-level DCAL: Designing a single microarchitecture that performs well across arbitrary program phases is a significant source of complexity. Core-level DCAL divides program behaviors into useful classes and provides dedicated core designs for these classes; the cores are streamlined for the targeted behaviors, enabling SPR to produce quality physical designs. (4) ISA-level DCAL: For portability across many different processors, mobile device software is often distributed using a virtual instruction-set-architecture (ISA) that does not correspond to any particular processor ISA. The prerequisite for translating the virtual ISA into a processor ISA on-the-fly opens the door to improvising on the processor's ISA for one or multiple core types, with the aim of further streamlining cores for SPR to generate quality physical designs.
The economic and societal benefits of DCAL are tangible. Automation accelerates innovation by allowing companies to focus more on developing richer user experiences and less on low-level technology that makes it all possible. Moreover, automation puts this technology into the hands of more people, including folks without niche expertise and small nimble design teams. Both companies and everyday users profit from the fact that more innovative products are being delivered to market sooner.
