Variability is a grand challenge that hinders the progress of semiconductor technology. Adaptive design is considered a promising approach for addressing this challenge, especially under increasingly tight chip power constraints. However, its application in practice is limited, largely due to the lack of systematic techniques for managing its overhead, complexity, and integration with existing design flows. This research will develop a design automation framework that optimizes the use of adaptivity resources, maximizes their efficiency, and balances the tradeoff with conventional design objectives. The key of this research is capturing the uncertainty and dynamics of adaptive designs in a lightweight manner, yet with high fidelity. New variability and adaptivity models will be investigated in conjunction with robust optimization methods. In addition, a formal technique will be studied to handle the tradeoffs among competing design objectives. Parallel computing techniques will also be explored to cope with the enormous problem sizes of current and emerging applications.
This research will strengthen some weak links in adaptive circuit technology and help pave a path toward its wide applications. It will simultaneously address variability and power challenges faced by nanometer semiconductor technologies. The potential improvement of chip power-efficiency will facilitate green computing technology. Furthermore, the proposed techniques will be applicable to next-generation device technologies and will therefore benefit the future of the semiconductor industry. This research will also serve as a test-bed for training students to understand synergies among various aspects of modern chip design processes.
