The distinction between computing and communication has blurred with the improvements in semiconductor technology as well as the speed and reliability of computer networks. At a macroscopic level, individuals increasingly rely upon smart phones, cloud computing, and similar infrastructure that combines computing systems with networking to accomplish their daily tasks. Advantages are realized from the seamless interconnection of computing systems and the network. Many end-users even consider the client device, the server, and the network as one unit that is used for productivity and/or entertainment. At the microscopic level, similar efficiencies present themselves when computing and networking blend. In an ideal case, the linkage between the two areas should not require the use of special-purpose software, because installing software on a network node to enable this blending can potentially cause the node to be unstable, more complex, and introduce security flaws. However, there is a significant challenge in linking the two domains without the use of additional software. This research focuses on understanding and characterizing the connection between the computing node and the network.
Since the internal components of a node are shared resources between all processes, including those that require network-based I/O, it is possible to infer the load on the internal components by observing variations in delay between successive network packets that are generated by the node. This inference materializes as a "delay signature," and can be used to blend the areas of architecture and networking. Specifically, this information can be used to develop algorithms for network security and management. For example, by simply probing a node and collecting its responses, it can be determined that the internal components (e.g., microprocessor) are heavily utilized. If the node is expected to be idle, this could be an indication that the node has been compromised and is running unauthorized software. This information can also be used for job scheduling in cluster grids. By monitoring Message Passing Interface (MPI) messages between grid nodes, the loads on the nodes can be determined without querying nodes directly. As a result, resource discovery messages are not needed. Another use of this information can be to predict system degradation and failure. As a node's resources become exhausted, the node generates a unique traffic pattern. This pattern is emitted prior to node failure and can be used to signal a switch to a secondary server.
This project uses a holistic approach that combines computer architecture and computer networking to investigate and characterize how the microarchitecture affects the network packet generation process. The delay signature provides information that can be attributed to the internal state and settings of the microarchitecture. Architectural settings, such as processor affinity, multi-threading, and power-saving modes, affect the delay signature. The PIs use a hardware testbed and a system simulator to characterize the basic mechanisms within the microprocessor that are manifested in the observable delay signature.
The investigators incorporate team-based laboratory projects within their computer architecture and computer networking courses to demonstrate the relationship between the two domains and to promote integrated learning by students in both areas. Potential applications of the delay signature include providing security for networked nodes by monitoring unauthorized utilization and increasing resiliency of a computing system by detecting patterns that predict a node failure.
The distinction between computing and communication has blurred with the improvements in semiconductor technology as well as the speed and reliability of computer networks. This research focused on understanding and characterizing the connection between the computing node and the network. One potential application of the results of this project is a non-invasive, network-based approach to counterfeit device / component detection. Since the internal components of a node are shared resources between all processes, including those that require network-based I/O, it is possible to infer the load on the internal components by observing variations in delay between successive network packets that are generated by the node. We conducted an extensive empirical analysis with field programmable gate arrays (FPGAs) to efficiently illustrate the effect that device components have on the network traffic that is produced by the device. The FPGA boards gave us the ability to emulate standard computing devices and the flexibility to easily change the configurations of the device. We captured and statistically analyzed the network traffic inter-arrival times of different traffic types. We find that, for various types of FPGAs, the inter-arrival time statistics are consistently different across various hardware configurations. We plan to investigate the implications of the phenomenon in future work.
