In the era beyond Moore's law, it will be imperative to consider improving resistance of integrated circuits to failures due to fabrication defects and variations, soft errors, and wearout as first-order considerations, to ensure economic viability of the semiconductor industry and robust operation of digital systems. This research will develop and demonstrate the benefits of a new multi-layered approach - spanning circuit, micro-architecture, instruction-set architecture, system, and user layers - for improving resistance to failures caused by fabrication, soft errors, and wearout. An approach to characterize user-layer impact of failures within each module will be developed to dramatically reduce overdesign and overtesting in future failure resistant systems. This research will also develop the first infrastructure to support systematic development of multi-layered approaches for failure resistance, including the first comprehensive models of layers, the first systematic method to identify candidate approaches and characterize their performance and overheads, and to derive globally optimal designs. This approach will identify efficient designs that will achieve failure resistance at uniquely low overheads.
The utilitarian gains to society should be immediate and and are likely to be substantial. The methods and tools developed will provide significant improvements in yield, performance, robustness to soft errors, and system lifespan. This project will train students and industry experts in the science and art of of efficient failure resistance, and prepare them for the era beyond the end of Moore's law. The principle investigator will also distribute to the community of researchers and industry experts the models, framework, and tools to be developed as a result of this project.
