Modern computer systems are undergoing a pervasive change. They are becoming increasingly parallel, meaning that multiple processing units, or cores, work together to carry out tasks. To facilitate the kinds of synchronization and coordination needed to exploit these new architectures, leading hardware vendors have developed a new generation of processor architectures that provide hardware transactional memory, a synchronization structure that promises to avoid many of the well-known pitfalls and limitations of conventional approaches to synchronization. The move to hardware transactions will bring about a fundamental positive change in the way multicore machines are programmed.
This project will redesign basic synchronization structures such as locks, memory management, and a range of concurrent data structures such as heaps, hash tables, and skip lists. These new structures will be embodied in an open-source C++ library. The project's goal is to create better performing, more reliable, and less expensive parallel software, scalable to larger systems, while at the same time making code simpler and more reliable. Moreover, this project will enhance understanding of how hardware transactional memory can be used effectively, a benefit to both users and manufacturers of future processors.
