The goal of this project is to develop energy efficient systems. Improving energy efficiency is a defining challenge for information technology and the prerequisite to increasing the capabilities of all computing systems, from smartphones to warehouse-scale data-centers. Most research in this area has focused on energy efficient computing, using specialized cores or near-threshold voltage circuits. To achieve end-to-end energy efficiency, the on-chip and off-chip memory system that feeds cores with data and instructions must also be optimized. The memory system includes large, leaking structures and communication operations that introduce energy overheads orders of magnitude higher than the overheads of compute operations.
This project proposes a holistic approach towards energy efficient memory systems that rethinks memory system architecture, dynamic runtime management, and circuit design. At the architecture level, it will optimize for emerging, data-centric applications with limited temporal locality by placing computing close to the memory structures so that energy intensive communication is minimized. It will also explore architectural support for specialization in the memory system, such as engines for specialized prefetch, data transformations, and data distribution. At the runtime management level, it will investigate scalable scheduling algorithms that minimize energy usage in the memory system by maximizing temporal and spatial locality and the use of on-chip and memory-side accelerators. At the circuit design level, it will aggressively optimize the energy consumption of the internal structures of memory chips and memory stacks for the dominant access patterns after efficient runtime management. Finally, this project will create tools for joint exploration of the architecture-management-scheduling space in order to identify Pareto optimal memory systems for different levels of performance.
