An important bottleneck for many parallel scientific applications is memory performance. Recently, vendors have introduced a new memory called high-bandwidth memory (HBM) as an approach to alleviate this bottleneck. This project will develop an algorithmic foundation for using HBM. The project has the potential for a broad economic, technological, and scientific impact, since industry has an investment in this technology and many of the nation's strategic codes are being run on HBM-capable machines. The PIs will integrate research with education at the graduate and undergraduate levels by training PhD, MS, and honors program BS students in cross-cutting issues encompassing algorithm design, high-performance software, and processor architecture.
The new approach offered by vendors is to bond memory (HBM) directly to the processor chip, which allows for more connections, enabling higher bandwidth. Although the size of the new memory is larger than modern on-chip caches, physical constraints limit the capacity of the memory to be significantly smaller than DRAM. HBM does not cleanly fit in the standard memory hierarchy. This project will develop a foundational understanding of how to algorithmically design codes for HBM enhanced architectures. Overcoming these intellectual challenges to achieve multi-core scalability using HBM requires new algorithms, models, and abstractions, spearheaded by this collaboration between researchers who study hardware issues, high performance computing challenges, and theoretical modeling and analysis.
