This project proposes a foundational approach to model-driven performance optimization of memory systems for modern computer architectures, with the development of a set of memory-architecture optimization methods and tools that are theoretically proven and empirically feasible for modern memory architecture design. The outcome of this project will significantly improve the performance modeling and optimization techniques for designing and evaluating memory architectures in modern computer systems, featuring deep and diverse memory-system hierarchies, heterogeneous memory devices, and complex data-intensive applications, including big-data, cloud and data centers and high-performance computing applications. The findings of this project will improve the content of various courses that the PIs teach. This project plans to proactively recruit minority students by taking advantage of the institutional efforts at IIT and especially at FIU, which is a minority-serving institution. This project will align education and outreach activities with an existing research and education center.
The growing disparity between CPU and memory speed causes memory accesses to become a severe performance bottleneck in modern computer architectures. Attempts to solving this ?memory wall? problem underpin technological innovations in computer-architecture design over the last two and half decades. The objective of the research is to significantly extend prior memory models and create a practical memory-architecture performance-modeling and optimization framework that can capture the combined effects of data locality, data concurrency, access latency, and multi-tier memory architecture for real applications and on real systems. A simulation-driven approach will be developed with elaborate real-system measurements and performance analyses to examine the potential benefits and identify the performance issues of various memory-architecture designs. More specifically, this project will develop along three research directions: (1) developing theoretical and architectural foundations to address both fundamental questions related to the tiered heterogeneous memory architectures and investigate practical aspects of applying the modeling and optimization framework for various memory architectures; (2) performing model-driven memory-architecture design and optimization for specific memory architectures, including disaggregated memory system, GPU, and deep-memory hierarchy with hybrid memory devices including non-volatile memory; and (3) developing the memory architecture simulator embedded with the performance modeling and optimization framework, and conducting simulation studies and real system measurements to evaluate memory performance, and compare design alternatives and trade-offs.
This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
