To attain significant improvements in yield with greater chip density, many semiconductor manufacturers have successfully employed redundancy techniques in the memory chip design, such as 64K DRAMs, 256K DRAMs, etc. Recently, due to the regular structure, Programmable Logic Arrays (PLAs) have become increasingly common for implementing Boolean logic functions in VLSI. This research is investigating an alternative PLA design with redundancy that will exploit the repairability of the partially defective chips in order to enhance the chip yield. The objectives of the research are to design and repair a fault-tolerant PLA and apply this design concept to any other array logic, such as programmable array logic (PAL), as well as Wafer-Scale Integration (WSI) design. The use of PLA structure, particularly in the control portion of a VLSI microprocessor, improves design productivity, shortens design time, simplifies the physical design of the chip, and facilitates the implementation of engineering changes. Semiconductor device manufacturers, continuously strive to increase chip complexity, reduce the speed-power product, increase reliability and produce useful and cost-effective devices. However, increasing the chip complexity would enhance the probability of having defective chips and then increase the cost. The proposed research will provide the new design and repair scheme to enhance the chip yields.
