This research is concerned with developing systematic, formal techniques for constructing VLSI systolic array architectures from machine independent algorithm descriptions. Emphasis is on adaptive filtering and matrix algebra algorithms since they are prevalent in modern signal processing. The research focuses on three elements: (1) techniques for synthesizing array interconnections and processing element operations based on the notion of activity charts; (2) the development of efficient processing element architectures examining the underlying kernel operations of the algorithms; and (3) the exploration of VLSI realizations for these processing elements with an emphasis on computation speed. The proposed research will extend and impact scientific knowledge related to the construction of systolic arrays and DSP (digital signal processing) architectures in several ways. Methods developed will increase the understanding of formal design techniques and could be the basis for a DSP systolic array compiler. Discovering the underlying rotational framework of DSP algorithms and enhancing general understanding of these algorithms is a potential outcome of this work. Finally, rapid computation of elementary functions is of paramount importance to fast computers. This project is developing VLSI architectures for fast rotation processors with multiplication and division as a subset.