The workshop addresses problems on defect tolerance and fault tolerance in complex VLSI (Very Large Scale Integration) and WSI (Wafer Scale Integration) systems. Its objective is to bring together researchers and designers in the above problem areas with developers of appropriate computer-aided design (CAD) tools and innovative packaging techniques. Its scope includes (a) defect and fault tolerant computer architectures; (b) defect and fault tolerant memories; (c) techniques for yield enhancements; (d) fault models and defect models; (e) statistical modeling of defects and yield; (f) repair and restructuring techniques; (g) packaging technologies for WSI and 3-D VLSI circuits; (h) high density hybrid circuits; (i) CAD tools; and (j) experimental systems. The research will bring together researchers and practitioners in both industry and academia in the U.S. and abroad to discuss problems on fabrication defects, yield models, and chip designs for yield enhancement. It will foster better interactions between industry and academia in understanding fabrication defects and developing defect tolerant and fault tolerant techniques and systems. The program committee consists of distinguished researchers in academia and industry. The workshop organizers have done extensive research in this area and are well respected in the problem areas addressed by the workshop. The grant funded by the National Science Foundation will be used to support travel for a keynote speaker and the printing cost of proceedings for conference attendees. Without the support from NSF, the cost of registration will be exceedingly high for the limited number of workshop attendees. Support is, therefore, highly recommended.
