This research addresses testing and fault analysis of complex VLSI (very large scale integrated) digital systems. Professor Hayes will develop new design techniques to enhance testability at the chip and system levels, and high-level methods for test generation. The research will exploit hierarchical structure and regularity inherent in most VLSI design, while recognizing that these characteristics deviate from the ideal. The major objective of Hayes' research is to understand how to achieve very high fault coverage and low test time for large VLSI circuits and systems. He will investigate testability characteristics of nearly regular VLSI chips. Methods of increasing the regularity of general types of nearly regular circuits to enhance their testability will be studied. A hierarchical approach to test generation that employs high-level circuit and fault models will be explored, and a study of the use of predetermined cell tests in testing of very high level circuits will be initiated. The principal investigator is an outstanding researcher with a solid record of accomplishments over the past decade, and he very likely will continue with first-class research. The proposal is technically sound, well conceived and on a good topic. This research is in an area important to industry, and is important to our understanding of design of VLSI circuits and systems.
