This research addresses the theoretical design, analysis and implementation of a VLSI chip for a neural-type cell. The neural-type cell has a number of properties that make it suitable for inclusion in a neural network; for example, an output pulse repetition rate controlled by input amplitude. The research is to: first, design, study and analyze the equations for the neural-type cell and obtain the device parameters which allow optimal size of hysteresis. Second, the VLSI layout for the circuit is being made and simulated to verify circuit characteristics. Plans include fabricating a VLSI chip based on the design, and integrating it into a neural network for performance measurement. This work is being done in conjunction with neural-net research at the University of Maryland.
