A new built-in self-test architecture that can better exploit parallel processing is being studied. In conventional built-in self-test algorithms, the pseudorandom pattern generators and signature registers do not operate in parallel. The goal of this research is to study a new built-in self-test architecture that generates the test pattern for one module while collecting responses of test patterns of other test modules. The resulting design will be area efficient, have parallel testing, and have simple control circuity. With the rapid growth of VLSI technology and increased complexity of VLSI circuits, conventional test methods in which the test patterns are stored in test equipment and are applied to the external pins of the chip may not be cost effective due to the poor accessibility to internal modes. With a built-in self-test scheme, test patterns and test response evaluators are placed in the same chip. The research of enhancing parallelism in built-in self-test is very important in complex VLSI circuits. The principal investigator is a new Ph.D. who already has significant progress in his research. The research focuses on important and timely topics. Support is highly recommended.
