The proposed work deals with application of parallel processing to communication systems problems, mostly with particular regard to implementation with the INMOS transputer device. There are three major areas with quite distinct objectives: (1) development of a high-speed simulator for analysis of digital communication systems, (2) investigation of new architecture ( generalized lattice) for implementation of digital filters, and (3) reformulation of signal processing algorithms typically used in communication systems ( least squares estimation, Kalman filtering, sequential decoding, etc.) for a more direct and efficient implementation as a form of systolic array. The objective of area (1) is to provide an effective analysis tool for designers of complex communication systems by virtue of the high computational speeds afforded by parallel processors. Areas (2) and (3) have similar objectives and represent an investigation of a more fundamental nature. The goal is to show ways to implement sophisticated signal processing operations (such as; bandpass filtering, Viterbi detection, adaptive channel equalization) at high speed so that communication channels can be utilized more efficiently. Another benefit of this work is the development of design tools for using an exisiting device ( the transputer) for implementing common signal processing operations.
