This research is on test and fault simulation algorithms that provide better fault coverage than the single-stuck-at (SSA) fault model. It is well known that faults occur in CMOS circuits that cannot be modeled by the traditional SSA fault model. This can lead to undetected physical faults, as well as inaccurate estimates of the product's defect level. The approach of Professor Ferguson is to use a software tool, FXT, which automates the concept of inductive fault analysis. He is characterizing realistic faults that occur in CMOS circuits, incorporating them into FXT and analyzing a wide variety of CMOS circuits. Computationally feasible testing procedures that detect those realistic CMOS faults are being developed and applied to real physical circuits to demonstrate compatibility of this testing approach with CMOS technology. Because of the increase in VLSI chip complexity, VLSI testing is becoming a critical aspect of IC manufacturing. This research investigates new concepts and algorithms for VLSI testing, which address detecting realistic physical faults in finished VLSI chips. The novelty is in the concepts that go beyond those in standard methods and should produce better tests for manufacturing faults. The principal investigator is a promising and competent young professor who should make significant contributions to the field.
